Modelsim inference bug. Observed on Questasim 2022.3 during vopt -O5.
Monitor in future releases.

Co-authored-by: Enrico Zelioli <ezelioli@iis.ee.ethz.ch>

* Remove `translate_off` directive from tc_sram_wrapper module (#22).
* Replace sram by sram_pulp: does not introduce cuts and allows for parametric byte width.
* Add HPDCache tc_sram wrappers.
* Add stub FPGA-specific memories: PULP CVA6 does *not* support the `FpgaEn` config option,
  as we want FPGA mappings to emulate taped-out designs as closely as possible.

Co-authored-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>
Co-authored-by: Luca Valente <68963253+luca-valente@users.noreply.github.com>

This commit disables X interface (i.e. sets the CvxifEn parameter to 0)
in all CVA6 configurations relevant to PULP projects.
If the X interface enabled and not used, it forwards illegal
instructions to a co-processor via the core X interface,
This leads to a stall if the X-interface is not connected to an actual
co-processor.
See `cvxif_compressed_if_driver` in `id_stage.sv`.

Co-authored-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>
Co-authored-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

* Bump FPU to pulp-v0.1.1
* Remove vendor folder in CVFPU
* Update Bender.lock
* cvfpu: Exclude util directory
* Bender.lock: Revert unrelated changes

Co-authored-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Co-authored-by: Enrico Zelioli <ezelioli@iis.ee.ethz.ch>

This reverts commit a27107b.

Experimental feature for some security research.

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

Co-authored-by: aottaviano <aottaviano@iis.ee.ethz.ch>
Co-authored-by: bluew <bluewww@users.noreply.github.com>
Co-authored-by: Enrico Zelioli <enricozelioli97@gmail.com>
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

Co-authored-by: msc22h2 <s290705@studenti.polito.it>
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

Completes support for self-invalidation coherence.
* std_cache: Pack valid/dirty SRAM
* std_cache: Decouple Valid/Dirty WE from Data WE

Co-authored-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

* Add Cheshire integration tests.
* Add PULP Gitlab CI.
* Track Bender.lock file.
* Deactivate 'stale' workflow.
* Do not trigger RISC-V tests on push.
* Report formatting issues via github annotations.
* Deactivate verible check for external repos due to security
concerns (`pull_request_target`)

Co-authored-by: Enrico Zelioli <ezelioli@iis.ee.ethz.ch>
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

Fix openhwgroup#1989